Typical functional verification systems, including hardware emulation systems and simulation acceleration systems, utilize interconnected programmable logic chips or interconnected processor chips. Examples of systems using programmable logic devices are disclosed in, for example, U.S. Pat. No. 6,009,256 entitled “Simulation/Emulation System and Method,” U.S. Pat. No. 5,109,353 entitled “Apparatus for emulation of electronic hardware system,” U.S. Pat. No. 5,036,473 entitled “Method of using electronically reconfigurable logic circuits,” U.S. Pat. No. 5,475,830) entitled “Structure and method for providing a reconfigurable emulation circuit without hold time violations,” and U.S. Pat. No. 5,960,191 entitled “Emulation system with time-multiplexed interconnect.” U.S. Pat. Nos. 6,009,256, 5,109,353, 5,036,473, 5,475,830, and 5,960,191 are incorporated herein by reference. Examples of hardware logic emulation systems using processor chips are disclosed in, for example, U.S. Pat. No. 6,618,698 “Clustered processors in an emulation engine,” U.S. Pat. No. 5,551,013 entitled “Multiprocessor for hardware emulation,” U.S. Pat. No. 6,035,117 entitled “Tightly coupled emulation processors,” and U.S. Pat. No. 6,051,030 entitled “Emulation module having planar array organization.” U.S. Pat. Nos. 6,618,698, 5,551,013, 6,035,117, and 6,051,030 which are incorporated herein by reference.
Visualization, also referred to as tracing, is an important feature in processor-based emulation systems. Visualization is the ability for a user to capture and observe the states of elements in the design being emulated. The ability to observe the state of every node (i.e., processor output) of a particular integrated circuit design, is an important feature for functional verification systems. Visualization is needed over certain periods of time, i.e., over a number of clock cycles. By capturing the internal states of the nodes during emulation, the user can observe the activity in the design being emulated and therefore be able to debug the design. Without the ability to observe the internal states of the nodes during emulation, it is more difficult for a user to understand the cause of any bugs in the design.
One mechanism to capture trace data has been through the use of a data capture card (DCC). A dedicated trace capture interface is provided to collect and capture trace signals into a DRAM of the data capture card for later upload to the workstation, where it can be reconstructed and displayed for the user. This mechanism provides the ability to capture the states of signals in the design while minimizing the use of regular emulation resources (virtual logic) for trace collection. This interface also provides for the ability to perform conditional acquisition of signal data by holding it in a trace array until it receives a control or trigger signal indicating whether the collected data should be transferred to the DCC, or discarded. The trace array may be a dual-ported SRAM, with a width large enough to accommodate the maximum possible capture bandwidth provided by any trace capture logic to be used.
According to some mechanisms, one of the outputs of an emulation processors data memory may have a dedicated connection to trace capture circuitry. The dedicated trace output would then be routed to the trace array and captured. Since typically up to around one-fourth of the emulation processor outputs represented the outputs of emulated flops, around one-fourth of all emulation processor evaluations would need to be captured in each emulation step to perform tracing. Because of the use of a dedicated output, the scheduler routed signals to the dedicated trace outputs of available emulation processors, which could extend the number of emulation steps needed to capture all the desired signals. There is also potentially wasted trace capacity since a single capture control signal was used to control all of the signals at once, preventing targeted recording of a subset of trace outputs. Thus, for at least these reasons there is a need for an improved method and apparatus for capturing trace data generated in a processor-based emulation system.